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HC08KL8GRS/D bảng dữ liệu(PDF) 84 Page - NXP Semiconductors

tên linh kiện HC08KL8GRS/D
Giải thích chi tiết về linh kiện  High-Performance M68HC08 Architecture
PDF  256 Pages
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System Integration Module (SIM)
General Release Specification
MC68HC08KL8 — Rev. 2.0
System Integration Module (SIM)
8.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. (See Figure
8-5.) An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, the USB module, or POR. (See Figure 8-6.) Note
that for POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in Figure
8-5.
Figure 8-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
Figure 8-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES
32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
USB
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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