HC08KL8GRSSLASHD datasheet(37/256 Pages) NXP

37 / 256 page

Memory Map

Input/Output (I/O) Section

MC68HC08KL8 — Rev. 2.0

General Release Specification

Memory Map

2.3 Input/Output (I/O) Section

Addresses $0000–$003F contain most of the control, status, and data

registers. Additional I/O registers have these addresses:

•

$FE00 (break status register, BSR)

•

$FE01 (reset status register, RSR)

•

$FE03 (break flag control register, BFCR)

•

$FE04 (interrupt status register 1, INT1)

•

$FE05 (interrupt status register 2, INT2)

•

$FE0C and $FE0D (break address registers, BRKH and BRKL)

•

$FE0E (break status and control register, BSCR)

•

$FFFF (COP control register, COPCTL)

2.4 Unimplemented Memory Locations

Some addresses are unimplemented. Accessing an unimplemented

address can cause an illegal address reset if illegal address resets are

enabled. In the memory map and in the I/O register summary,

unimplemented addresses are shaded.

Some I/O bits are read-only: the write function is unimplemented. Writing

to a read-only I/O bit has no effect on MCU operation. In register figures,

the write function of read-only bits is shaded.

2.5 Reserved Memory Locations

Some addresses are reserved. Writing to a reserved address can have

unpredictable effects on MCU operation. In the memory map and in the

I/O register summary, reserved addresses are marked with the word

Reserved.

Some I/O bits are reserved. Writing to a reserved bit can have

unpredictable effects on MCU operation. In register figures, reserved

bits are marked with the letter R.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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