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HC08KL8GRS/D bảng dữ liệu(PDF) 83 Page - NXP Semiconductors

tên linh kiện HC08KL8GRS/D
Giải thích chi tiết về linh kiện  High-Performance M68HC08 Architecture
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System Integration Module (SIM)
Reset and System Initialization
MC68HC08KL8 — Rev. 2.0
General Release Specification
System Integration Module (SIM)
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 8.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 8.8 SIM Registers.)
8.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 CGMXCLK cycles, assuming that the POR was not the source of the
reset. See Table 8-2 for details. Figure 8-4 shows the relative timing.
Figure 8-4. External Reset Timing
Table 8-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR
4163 (4096 + 64 + 3)
All Others
67 (64 + 3)
RST
IAB
PC
VECT H
VECT L
CGMOUT
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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