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STM32W108HB bảng dữ liệu(PDF) 65 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 65 Page - STMicroelectronics |
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65 / 278 page  STM32W108HB STM32W108CC STM32W108CB STM32W108CZ System modules Doc ID 16252 Rev 14 65/278 Sleep timer compare A low register (SLPTMR_CMPAL) Address: 0x4000 601C Reset value: 0x0000 FFFF Reserved, must be kept at reset value CMPAL[15:0]: Sleep timer compare A low value Sleep timer compare B high register (SLPTMR_CMPBH) Address: 0x4000 6020 Reset value: 0x0000 FFFF Reserved, must be kept at reset value CMPBH[15:0]: Sleep timer compare B high value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMPAL[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:16] Bits [15:0] Writing to this register puts the value in the hold register until a write to the SLPTMR_CMPAH register. The value can only be changed when the sleep timer is disabled (EN bit set to ‘0’ in the SLPTMR_CR register). If the value is changed when the sleep timer is enabled (EN bit set to ‘1’ in the SLPTMR_CR register) a spurious interrupt may be generated. Therefore it is recommended to disable interrupts before changing this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMPBH[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:16] Bits [15:0] Sleep timer compare value - writing to this register updates the SLPTMR_CMPBH register directly and updates the SLPTMR_CMPBL register from the hold register. This value can only be changed when the EN (bit 11 of SLPTMR_CR register) is set to ‘0’. If the value is changed when the EN bit is set to ‘1’, a spurious interrupt may be generated. Therefore it is recommended to disable interrupts before changing this register. |
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