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STM32W108HB bảng dữ liệu(PDF) 60 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 60 Page - STMicroelectronics |
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60 / 278 page  System modules STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 60/278 Doc ID 16252 Rev 14 6.4.4 Event timer The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK is either the SCLK or PCLK as selected by CLK_CPUCR (see Section 6.3.5: Clock switching on page 51). 6.4.5 Slow timer (MAC timer, Watchdog, and Sleeptimer) control and status registers These registers are powered from the always-on power domain. All registers are only writable when in System mode MACTimer counter register (MACTMR_CNTR) Address: 0x4000 2038 Reset value: 0x0000 0000 Reserved, must be kept at reset value CNT[19:0]: MAC timer counter value MACTimer counter register (MACTMR_CR) Address: 0x4000 208C Reset value: 0x0000 0000 Reserved, must be kept at reset value RST: MAC timer reset EN: MAC timer enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CNT[19:16] rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:20] Bits [19:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RST EN rw rw Bits [31:2] Bit 1 Bit 0 |
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