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STM32W108HB bảng dữ liệu(PDF) 63 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 63 Page - STMicroelectronics |
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63 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ System modules Doc ID 16252 Rev 14 63/278 Sleep timer count high register (SLPTMR_CNTH) Address: 0x4000 6010 Reset value: 0x0000 0000 Reserved, must be kept at reset value CNTH[15:0]: Sleep timer counter high value Bit 10 DBGP: Debug pause 0: The timer continues working in Debug mode. 1: The timer is paused in Debug mode when the CPU is halted. Bits [9:8] Reserved, must be kept at reset value Bits [7:4] PSC[3:0]: Sleep timer prescaler setting Divides clock by 2N where N = 0 to 15. Can only be changed when the EN is set to ‘0’. Bits [3:1] Reserved, must be kept at reset value Bit 0 CLKSEL: Clock select 0: Calibrated 1kHz RC clock (default); 1: 32kHz. Can only be changed when the EN is set to ‘0’. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNTH[15:0] rrr rrr r r r r r r r r r r Bits [31:16] Bits [15:0] Reading this register updates the SLEEP_CNTL for subsequent reads. |
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