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STM32W108HB bảng dữ liệu(PDF) 62 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 62 Page - STMicroelectronics |
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62 / 278 page ![]() System modules STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 62/278 Doc ID 16252 Rev 14 Watchdog kick-start register (WDG_KICKSR) Write any value to this register to kick-start the watchdog. Address: 0x4000 6008 Reset value: 0x0000 0000 Reserved, must be kept at reset value KS[15:0]: Sleep timer configuration register (SLPTMR_CR) This register sets the various options for the Sleep timer. Address: 0x4000 600C Reset value: 0x0000 0400 REVERSE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KS[15:0] w wwww w w w w w w w w w w w Bits [31:16] Bits [15:0] Watchdog kick-start value: write any value to restart the watchdog. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EN DBGP Reserved PSC[3:0] Reserved CLK SEL rw rw rw rw rw rw rw rw Bits [31:13] Reserved, must be kept at reset value Bit 12 REVERSE: 0: Count forward 1: Count backwards Only changes when EN is set to ‘0’ Bit 11 EN: 0: Disable sleep timer 1: Enable sleep timer To change other register bits (REVERSE, PSC, CLKSEL), this bit must be set to ‘0’. Enabling/Disabling latency can be up 2 to 3 clock-periods of selected clock. |
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