STM32W108HB datasheet(45/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

System modules

Doc ID 16252 Rev 14

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Deep sleep reset

The Power Management module informs the Reset Generation module of entry into and exit

from the deep sleep states. The deep sleep reset is applied in the following states: before

entry into deep sleep, while removing power from the memory and core domain, while in

deep sleep, while waking from deep sleep, and while reapplying power until reliable power

levels have been detect by POR LV.

The Power Management module allows a special emulated deep sleep state that retains

memory and core domain power while in deep sleep.

6.2.2

Reset recording

The STM32W108 records the last reset condition that generated a restart to the system.

The reset conditions recorded are:

●

PWRHV

Always-on domain power supply failure

●

PWRLV

Core or memory domain power supply failure

●

RSTB

NRST pin asserted

●

WDG

Watchdog timer expired

●

SWRST

Software reset by SYSERSETREQ from ARM® Cortex-M3

CPU

●

WKUP

Wake-up from deep sleep

●

OBFAIL

Error check failed when reading option bytes from Flash

memory

The Reset status register (RST_SR) is used to read back the last reset event. All bits are

mutually exclusive except the OBFAIL bit which preserves the original reset event when set.

Note:

While CPU Lockup is marked as a reset condition in software, CPU Lockup is not

specifically a reset event. CPU Lockup is set to indicate that the CPU entered an

unrecoverable exception. Execution stops but a reset is not applied. This is so that a

debugger can interpret the cause of the error. We recommend that in a live application (i.e.

no debugger attached) the watchdog be enabled by default so that the STM32W108 can be

restarted.

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