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STM32W108HB bảng dữ liệu(PDF) 46 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 46 Page - STMicroelectronics |
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46 / 278 page ![]() System modules STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 46/278 Doc ID 16252 Rev 14 6.2.3 Reset generation The Reset Generation module responds to reset sources and generates the following reset signals: ● PORESET Reset of the ARM® Cortex-M3 CPU and ARM® Cortex-M3 System Debug components (Flash Patch and Breakpoint, Data Watchpoint and Trace, Instrumentation Trace Macrocell, Nested Vectored Interrupt Controller). ARM defines PORESET as the region that is reset when power is applied. ● SYSRESET Reset of the ARM® Cortex-M3 CPU without resetting the Core Debug and System Debug components, so that a live system can be reset without disturbing the debug configuration. ● DAPRESET Reset to the SWJ's AHB Access Port (AHB-AP). ● PRESETHV Peripheral reset for always-on power domain, for peripherals that are required to retain their configuration across a deep sleep cycle. ● PRESETLV Peripheral reset for core power domain, for peripherals that are not required to retain their configuration across a deep sleep cycle. Table 6 shows which reset sources generate certain resets. POR HV POR LV (in deep sleep) POR LV (not in deep sleep) RSTB Watchdog reset Software reset Option byte error Normal deep sleep Emulated deep sleep Debug reset Table 6. Generated resets Reset source Reset generation PORESET SYSRESET DAPRESET PRESETHV PRESETLV XXX XX XXX X XXX XX XX XX XX X XX X XX X XXX X XX X |
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