ST7LUS5 datasheet(43/124 Pages) STMICROELECTRONICS

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ST7LUS5, ST7LU05, ST7LU09

Interrupts

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7.4.2

SI register description

System integrity (SI) control/status register (SICSR)

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset

can be detected by software while an external reset can not.

SICSR

Reset value: 0000 0x00 (0xh)

654

Reserved

CR[1:0]

Reserved

LVDRF

Reserved

R/W

Table 19.

SICSR register description

Bit

Name

Function

Reserved, must be kept cleared.

6:5 CR[1:0]

RC Oscillator Frequency Adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written

immediately after reset to adjust the RC oscillator frequency and to obtain the

required accuracy. Refer to Section 6.1 on page 27.

4:3

Reserved, must be kept cleared

LVDRF

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared when read. See WDGRF flag description in

Section 10.1 for more details. When the LVD is disabled by option byte, the LVDRF

bit value is undefined.

Note: If the selected clock source is one of the two internal ones, and if VDD

remains below the selected LVD threshold during less than TAWU (33µs typ.), the

LVDRF flag cannot be set even if the device is reset by the LVD.

If the selected clock source is the external clock (CLKIN), the flag is never set if the

reset occurs during Halt mode. In Run mode the flag is set only if fCLKIN is greater

than 10 MHz.

1:0

Reserved, must be kept cleared

Table 20.

System integrity register map and reset values

Address

(Hex.)

Label

76543

210

003Ah

SICSR

Reset value

01100

LVDRF

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