ST7LUS5 datasheet(51/124 Pages) STMICROELECTRONICS

51 / 124 page

ST7LUS5, ST7LU05, ST7LU09

Power saving modes

51/124

instruction. The main reason for this is that the I/O may be wrongly configured due to

external interference or by an unforeseen logical condition.

●

For the same reason, re-initialize the level sensitiveness of each external interrupt as a

precautionary measure.

●

The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

due to a program counter failure, it is advised to clear all occurrences of the data value

0x8E from memory. For example, avoid defining a constant in ROM with the value

0x8E.

●

As the HALT instruction clears the I bit in the CC register to allow interrupts, the user

may choose to clear all pending interrupt bits before executing the HALT instruction.

This avoids entering other peripheral interrupt routines after executing the external

interrupt routine corresponding to the wake-up event (reset or external interrupt).

8.5

Auto Wake-up from Halt mode

Auto Wake-up from Halt (AWUFH) mode is similar to Halt mode with the addition of a

specific internal RC oscillator for wake-up (Auto Wake-up from Halt oscillator) which

replaces the main clock which was active before entering Halt mode. Compared to Active

Halt mode, AWUFH has lower power consumption (the main clock is not kept running), but

there is no accurate real-time clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR

Figure 23.

AWUFH mode block diagram

As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR

a fixed divider and a programmable prescaler controlled by the AWUPR register. The output

of this prescaler provides the delay time. When the delay has elapsed, the following actions

are performed:

●

the AWUF flag is set by hardware,

●

an interrupt wakes up the MCU from Halt mode,

●

the main oscillator is immediately turned on and the 64 CPU cycle delay is used to

stabilize it.

After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The

AWU flag and its associated interrupt are cleared by software reading the AWUCSR

AWU RC

AWUFH

fAWU_RC

AWUFH

(ei0 source)

oscillator

prescaler/1 .. 255

interrupt

/64

divider

to 8-bit Timer input capture

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