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ST7LUS5 bảng dữ liệu(PDF) 93 Page - STMicroelectronics |
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ST7LUS5 bảng dữ liệu(HTML) 93 Page - STMicroelectronics |
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93 / 124 page ![]() ST7LUS5, ST7LU05, ST7LU09 Electrical characteristics 93/124 Figure 37. fCLKIN maximum operating frequency versus VDD supply voltage Table 65. Operating conditions with low voltage detector (LVD)(1) 1. TA = -40 to 125°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) High threshold 3.50 4.00 4.50 V VIT-(LVD) Reset generation threshold (VDD fall) 3.30 3.80 4.40 Vhys LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 150 mV VtPOR VDD rise time rate (2)(3) 2. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset release. When the VDD slope is outside these values, the LVD may not release properly the reset of the MCU. 3. Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 56 on page 109. 20 - µs/V IDD(LVD) (4) 4. Not tested in production LVD current consumption VDD = 5V 220 µA fCLKIN [MHz] SUPPLY VOLTAGE [V] 16 8 4 0 2.0 3.0 3.5 4.0 4.5 5.0 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 5.5 FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA) 2.7 3.3 |
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