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ST7LUS5 bảng dữ liệu(PDF) 53 Page - STMicroelectronics |
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ST7LUS5 bảng dữ liệu(HTML) 53 Page - STMicroelectronics |
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53 / 124 page ![]() ST7LUS5, ST7LU05, ST7LU09 Power saving modes 53/124 Figure 25. AWUFH mode flowchart 1. WDGHALT is an option bit. See option bytes in Section 14.1.1: Flash configuration for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 15: Interrupt mapping on page 39 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. RESET INTERRUPT(3) Y N N Y CPU MAIN OSC PERIPHERALS(2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU MAIN OSC PERIPHERALS I[1:0] BITS ON OFF XX(4) ON CPU MAIN OSC PERIPHERALS I[1:0] BITS ON ON XX(4) ON 64 CPU CLOCK DELAY WATCHDOG ENABLE DISABLE WDGHALT(1) 0 WATCHDOG RESET 1 CYCLE AWU RC OSC ON AWU RC OSC OFF AWU RC OSC OFF HALT INSTRUCTION (Active Halt disabled) (AWUCSR.AWUEN=1) |
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