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ST7LUS5 bảng dữ liệu(PDF) 61 Page - STMicroelectronics |
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ST7LUS5 bảng dữ liệu(HTML) 61 Page - STMicroelectronics |
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61 / 124 page  ST7LUS5, ST7LU05, ST7LU09 I/O ports 61/124 9.6 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 27. Interrupt I/O port state transitions The I/O port register configurations are summarized in the following table: Note: After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0 and MUXCR1 registers. See Section 6.4 on page 36. Table 31. Port configuration Port Pin name Input (DDR=0) Output (DDR=1) OR = 0 OR = 1 OR = 0 OR = 1 Port A PA0:2, PA4:5 floating pull-up interrupt open drain push-pull PA3 - - open drain push-pull Table 32. I/O port register map and reset values Address (Hex.) Register label 7654 3210 0000h PADR Reset value MSB 0000 000 LSB 0 0001h PADDR Reset value MSB 0000 100 LSB 0 0002h PAOR Reset value MSB 0000 001 LSB 0 01 floating/pull-up interrupt INPUT 00 floating (reset state) INPUT 10 open-drain OUTPUT 11 push-pull OUTPUT XX = DDR, OR |
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