NRF9160-SICA-R7 datasheet(262/400 Pages) NORDIC

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Peripherals

FLASHREGION[0].PERM

FLASHNSC[0].REGION == n

Access

control

FLASHREGION[n].PERM

SPU registers

Region #n

(secure)

NSC subregion 0

FLASHNSC[0].SIZE == m

m !=0

Region size

Flash address space

Region #n-1

Region #n+1

2(m+4) bytes

Figure 82: Non-secure callable region definition in the flash memory space

The NSC sub-region will only be defined if:

• FLASHNSC[i].SIZE value is non zero

• FLASHNSC[i].REGION defines a secure region

If FLASHNSC[i].REGION and FLASHNSC[j].REGION have the same value, there is only one sub-region

defined as NSC, with the size given by the maximum of FLASHNSC[i].SIZE and FLASHNSC[j].SIZE.

If FLASHNSC[i].REGION defines a non-secure region, then there is no non-secure callable region defined

and the selected region stays non-secure.

6.15.2.2 Flash access error reporting

The SPU and the logic controlled by it will respond with a certain behavior once an access violation is

detected.

The following will happen once the logic controlled by the SPU detects an access violation on one of the

flash ports:

• The faulty transfer will be blocked

• In case of a read transfer, the bus will be driven to zero

• Feedback will be sent to the master through specific bus error signals, if this is supported by the

master. Moreover, the SPU will receive an event that can optionally trigger an interrupt towards the

CPU.

• SecureFault exception will be triggered if security violation is detected for access from Cortex-M33

• BusFault exception will be triggered when read/write/execute protection violation is detected for

Cortex-M33

• FLASHACCERR event will be triggered if any access violations are detected for all master types except

for Cortex-M33 security violation

The following table summarizes the SPU behavior based on the type of initiator and access violation:

4418_1315 v2.0

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