NRF9160-SICA-R7 datasheet(45/400 Pages) NORDIC

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Application core

4.7 EasyDMA

EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.

EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for

direct access to Data RAM. EasyDMA is not able to access flash.

A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example,

for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA

example on page 45.

Peripheral

READER

Peripheral

Core

AHB Multilayer

AHB

WRITER

AHB

RAM

EasyDMA

Figure 5: EasyDMA example

An EasyDMA channel is implemented in the following way, but some variations may occur:

READERBUFFER_SIZE 5

WRITERBUFFER_SIZE 6

uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000;

uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;

// Configuring the READER channel

MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;

MYPERIPHERAL->READER.PTR = &readerBuffer;

// Configure the WRITER channel

MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;

MYPERIPHERAL->WRITER.PTR = &writerBuffer;

This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for

reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed

that the peripheral will perform the following tasks:

• Read 5 bytes from the readerBuffer located in RAM at address 0x20000000

• Process the data

• Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005

The memory layout of these buffers is illustrated in EasyDMA memory layout on page 46.

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