NRF9160-SICA-R7 datasheet(20/400 Pages) NORDIC

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4 Application core

4.1 CPU

The ARM Cortex-M33 processor has a 32-bit instruction set (Thumb-2 technology) that implements a

superset of 16 and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance

signal processing, including:

• Digital signal processing (DSP) instructions

• Single-cycle multiply and accumulate (MAC) instructions

• Hardware divide

• 8- and 16-bit single instruction, multiple data (SIMD) instructions

• Single-precision floating-point unit (FPU)

• Memory Protection Unit (MPU)

• ARM TrustZone for ARMv8-M

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the

ARM Cortex processor series is implemented and available for the M33 CPU.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling

events at configurable priority levels via the nested vectored interrupt controller (NVIC).

Executing code from internal or external flash will have a wait state penalty. The instruction cache can

be enabled to minimize flash wait states when fetching instructions. For more information on cache,

see Cache on page 31. The section Electrical specification on page 21 shows CPU performance

parameters including the wait states in different modes, CPU current and efficiency, and processing power

and efficiency based on the CoreMark benchmark.

4.1.1 CPU and support module configuration

The ARM Cortex-M33 processor has a number of CPU options and support modules implemented on the

device.

4418_1315 v2.0

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