NRF9160-SICA-R7 datasheet(46/400 Pages) NORDIC

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Application core

readerBuffer[0]

readerBuffer[1]

readerBuffer[2]

readerBuffer[3]

readerBuffer[4]

writerBuffer[0]

writerBuffer[1]

writerBuffer[2]

writerBuffer[3]

writerBuffer[4]

writerBuffer[5]

0x20000000

0x20000004

0x20000008

Figure 6: EasyDMA memory layout

The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer

(writerBuffer). Otherwise, the channel would overflow the writerBuffer.

Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many

bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how

many bytes WRITER wrote to RAM.

Note: The PTR register of a READER or WRITER must point to a valid memory region before use.

The reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page

21 for more information about the different memory regions and EasyDMA connectivity.

4.7.1 EasyDMA error handling

Some errors may occur during DMA handling.

If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result

in a HardFault or RAM corruption. See Memory on page 21 for more information about the different

memory regions.

If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might

occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall

and wait for access to be granted, or lose data.

4.7.2 EasyDMA array list

EasyDMA is able to operate in Array List mode.

The Array List mode is implemented in channels where the LIST register is available.

The array list does not provide a mechanism to explicitly specify where the next item in the list is located.

Instead, it assumes that the list is organized as a linear array where items are located one after the other

in RAM.

4418_1315 v2.0

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