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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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NRF9160-SICA-R7 bảng dữ liệu(PDF) 97 Page - Nordic Semiconductor |
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NRF9160-SICA-R7 bảng dữ liệu(HTML) 97 Page - Nordic Semiconductor |
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97 / 400 page  Peripherals 6.3.1.6 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID P O N M L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A-P RW TRIGGERED[i] (i=0..15) Write '1' to enable interrupt for event TRIGGERED[i] Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.3.1.7 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID P O N M L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A-P RW TRIGGERED[i] (i=0..15) Write '1' to disable interrupt for event TRIGGERED[i] Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.3.2 Electrical specification 6.3.2.1 EGU Electrical Specification Symbol Description Min. Typ. Max. Units tEGU,EVT Latency between setting an EGU event flag and the system setting an interrupt 1 cycles 6.4 GPIO — General purpose input/output The general purpose input/output pins (GPIOs) are grouped as one or more ports with each port having up to 32 GPIOs. The number of ports and GPIOs per port may vary with product variant and package. Refer to Registers on page 101 and Pin assignments on page 385 for more information about the number of GPIOs that are supported. GPIO has the following user-configurable features: • Up to 32 GPIO pins per GPIO port • Configurable output drive strength • Internal pull-up and pull-down resistors • Wake-up from high or low level triggers on all pins 4418_1315 v2.0 97 |
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