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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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NRF9160-SICA-R7 bảng dữ liệu(PDF) 257 Page - Nordic Semiconductor |
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NRF9160-SICA-R7 bảng dữ liệu(HTML) 257 Page - Nordic Semiconductor |
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257 / 400 page  Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A RW DEF Default character. Character clocked out in case of an ignored transaction. 6.14.6.41 ORC Address offset: 0x5C0 Over-read character Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A RW ORC Over-read character. Character clocked out after an over-read of the transmit buffer. 6.14.7 Electrical specification 6.14.7.1 SPIS slave interface electrical specifications Symbol Description Min. Typ. Max. Units fSPIS Bit rates for SPIS15 816 Mbps tSPIS,START Time from RELEASE task to receive/transmit (CSN active) 0.125 µs 6.14.7.2 Serial Peripheral Interface Slave (SPIS) timing specifications Symbol Description Min. Typ. Max. Units tSPIS,CSCKIN SCK input period 125 ns tSPIS,RFSCKIN SCK input rise/fall time 30 ns tSPIS,WHSCKIN SCK input high time 30 ns tSPIS,WLSCKIN SCK input low time 30 ns tSPIS,SUCSN CSN to CLK setup time 1000 ns tSPIS,HCSN CLK to CSN hold time 2000 ns tSPIS,ASA CSN to MISO driven 0 ns tSPIS,ASO CSN to MISO valida 1000 ns tSPIS,DISSO CSN to MISO disableda 68 ns tSPIS,CWH CSN inactive time 300 ns tSPIS,VSO CLK edge to MISO valid 19 ns tSPIS,HSO MISO hold time after CLK edge 1817 ns tSPIS,SUSI MOSI to CLK edge setup time 59 ns tSPIS,HSI CLK edge to MOSI hold time 20 ns 15 High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 16 The actual maximum data rate depends on the master's CLK to MISO and MOSI setup and hold timings. a At 25pF load, including GPIO capacitance, see GPIO spec. 17 This is to ensure compatibility to SPI masters sampling MISO on the same edge as MOSI is output 4418_1315 v2.0 257 |
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