NRF9160-SICA-R7 datasheet(199/400 Pages) NORDIC

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Peripherals

SAR

core

Internal reference

VDD_GPIO

REFSEL

RESP

RESN

AIN2

AIN3

AIN0

AIN1

AIN6

AIN7

AIN4

AIN5

MUX

VDD_GPIO

AIN2

AIN3

AIN0

AIN1

AIN6

AIN7

AIN4

AIN5

MUX

VDD_GPIO

PSEL_A

CH[X].PSELP

PSEL_A

CH[X].PSELN

PSEL_A

CH[X].CONFIG

ADC

GAIN

RAM

RESULT

EasyDMA

RESULT.PTR

START

SAMPLE

STOP

STARTED

END

STOPPED

Figure 65: Simplified ADC block diagram

Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with

single-ended input in the MODE field of the CH[n].CONFIG register. In single-ended mode, the negative

input will be shorted to ground internally.

The assumption in single-ended mode is that the internal ground of the ADC is the same as the external

ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB in

single-ended mode. If this is a concern we recommend using differential measurement.

6.12.2 Digital output

The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as

follows:

RESULT = [V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION - m)

where

V(P)

is the voltage at input P

V(N)

is the voltage at input N

GAIN

is the selected gain setting

is the mode setting. Use m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff

REFERENCE

is the selected reference voltage

The result generated by the ADC will deviate from the expected due DC errors like offset, gain, differential

non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these

parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors

4418_1315 v2.0

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