NRF9160-SICA-R7 datasheet(165/400 Pages) NORDIC

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Peripherals

6.10.2 Decoder with EasyDMA

The decoder uses EasyDMA to take PWM parameters stored in RAM and update the internal compare

registers of the wave counter, based on the mode of operation.

PWM parameters are organized into a sequence containing at least one half word (16 bit). Its most

significant bit[15] denotes the polarity of the OUT[n] while bit[14:0] is the 15-bit compare value.

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

B A A A A A A A A A A A A A A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

RW COMPARE

Duty cycle setting - value loaded to internal compare

RW POLARITY

Edge polarity of GPIO.

RisingEdge

First edge within the PWM period is rising

FallingEdge

First edge within the PWM period is falling

The DECODER register controls how the RAM content is interpreted and loaded into the internal compare

registers. The LOAD field controls if the RAM values are loaded to all compare channels, or to update a

group or all channels with individual values. The following figure illustrates how parameters stored in RAM

are organized and routed to various compare channels in different modes:

COMPARE

...

COMPARE

COMP0

COMP1

COMP2

COMP3

SEQ[n].PTR

COMP0

COMP1

COMP2

COMP3

COMP0

COMP1

COMP2

COMP3

DECODER.LOAD=Common

COMPARE

...

COMPARE

COMP0

COMP1

COMP2

COMP3

COMP0

COMP1

DECODER.LOAD=Grouped

COMPARE

COMP0

COMP1

COMP3

DECODER.LOAD=Single

COMPARE

COMP2

Increasing Data

RAM address

COMPARE

TOP

COMP0

COMP1

COUNTERTOP

DECODER.LOAD=WaveForm

COMPARE

COMP2

Figure 45: Decoder memory access modes

A special mode of operation is available when DECODER.LOAD is set to WaveForm. In this mode, up to

three PWM channels can be enabled - OUT[0] to OUT[2]. In RAM, four values are loaded at a time: the

first, second and third location are used to load the values, and the fourth RAM location is used to load

the COUNTERTOP register. This way one can have up to three PWM channels with a frequency base that

changes on a per PWM period basis. This mode of operation is useful for arbitrary wave form generation

in applications, such as LED lighting.

The register SEQ[n].REFRESH=N (one per sequence n=0 or 1) will instruct a new RAM stored pulse width

value on every (N+1)th PWM period. Setting the register to zero will result in a new duty cycle update

every PWM period, as long as the minimum PWM period is observed.

4418_1315 v2.0

165

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