NRF9160-SICA-R7 datasheet(160/400 Pages) NORDIC

160 / 400 page

Peripherals

6.9.7.22 SAMPLE.PTR

Address offset: 0x560

RAM address pointer to write samples to with EasyDMA

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Field

Value ID

Value

Description

SAMPLEPTR

Address to write PDM samples to over DMA

Note: See the memory chapter for details about which

memories are available for EasyDMA.

6.9.7.23 SAMPLE.MAXCNT

Address offset: 0x564

Number of samples to allocate memory for in EasyDMA mode

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A A A A A A A A A A A A A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Field

Value ID

Value

Description

BUFFSIZE

[0..32767]

Length of DMA RAM allocation in number of samples

6.9.8 Electrical specification

6.9.8.1 PDM Electrical Specification

Symbol

Description

Min.

Typ.

Max.

Units

fPDM,CLK,64

PDM clock speed. PDMCLKCTRL = Default (Setting needed

for 16 MHz sample frequency @ RATIO = Ratio64)

1.032

MHz

fPDM,CLK,80

PDM clock speed. PDMCLKCTRL = 1280K (Setting needed

for 16 MHz sample frequency @ RATIO = Ratio80)

1.28

MHz

tPDM,JITTER

Jitter in PDM clock output

TdPDM,CLK

PDM clock duty cycle

tPDM,DATA

Decimation filter delay

tPDM,cv

Allowed clock edge to data valid

125

tPDM,ci

Allowed (other) clock edge to data invalid

tPDM,s

Data setup time at fPDM,CLK=1.024 MHz or 1.280 MHz

tPDM,h

Data hold time at fPDM,CLK=1.024 MHz or 1.280 MHz

GPDM,default

Default (reset) absolute gain of the PDM module

3.2

4418_1315 v2.0

160

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