NRF9160-SICA-R7 datasheet(120/400 Pages) NORDIC

120 / 400 page

Peripherals

• 8, 16 and 24-bit sample width

• Low-jitter Master Clock generator

• Various sample rates

I2S

TXD.PTR

RXD.PTR

RXTXD.MAXCNT

PSEL.SCK

PSEL.LRCK

PSEL.MCK

PSEL.SDIN

Master clock

generator

CONFIG.MCKEN

CONFIG.MCKFREQ

Serial tranceiever

PSEL.SDOUT

CONFIG.MODE

CONFIG.FORMAT

CONFIG.RATIO

CONFIG.ALIGN

Div

RAM

MCK

EasyDMA

Figure 23: I2S master

6.7.1 Mode

The I2S protocol specification defines two modes of operation, Master and Slave.

The I2S mode decides which of the two sides (Master or Slave) shall provide the clock signals LRCK and

SCK, and these signals are always supplied by the Master to the Slave.

6.7.2 Transmitting and receiving

The I2S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial

data is shifted synchronously to the clock signals SCK and LRCK.

TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on

the rising edge of SCK. The most significant bit (MSB) is always transmitted first.

Note: When starting a transmission in master mode, two frames (two left-and-right sample pairs)

of value zero will be transmitted after triggering the START task, prior to the RXTXD.MAXCNT

samples specified by the TXD.PTR pointer.

TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in

the CONFIG.TXEN on page 134 and CONFIG.RXEN on page 134.

Transmission and/or reception is started by triggering the START task. When started and transmission

is enabled (in CONFIG.TXEN on page 134), the TXPTRUPD event will be generated for every

RXTXD.MAXCNT on page 137 number of transmitted data words (containing one or more samples).

4418_1315 v2.0

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