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PI7C9X760ACLEX bảng dữ liệu(PDF) 30 Page - Diodes Incorporated

tên linh kiện PI7C9X760ACLEX
Giải thích chi tiết về linh kiện  I2C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs
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nhà sản xuất  DIODES [Diodes Incorporated]
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PI7C9X760ACLEX bảng dữ liệu(HTML) 30 Page - Diodes Incorporated

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www.diodes.com
April 2019
Diodes Incorporated
PI7C9X760
Document Number DS40305 Rev 6-2
A product Line of
Diodes Incorporated
PI7C9X760
Offset 04H: XON1 character Register (XON1). Accessible when LCR=0xBF and SFR[2]=0. Default=00
Bit
Type
Description
[7:0]
RW
XON1 character
Note: It is reset only when Power-On-Reset.
Offset 05H: Line Status Register (LSR). Accessible when LCR[7]=0. Default=60
Bit
Type
Description
7
RO
Receiver FIFO Data Error Flag.
0 = No FIFO Error
1 = a flag for the sum of all error bits (parity error, framing error, or break) in the RX FIFO. This bit
clears when there is no more error in any of the bytes in the RX FIFO.
6
RO
THR and TSR Empty Flag
This bit is set whenever the transmitter goes idle, it clears whenever either the THR or TSR contains a
data character.
5
RO
THR Empty Flag
This bit is set when the last data byte is transferred from THR to TSR.
4
RO
Receiver Break Error Flag
0 = No Break Error
1 = break condition occurred in data to be read from RX FIFO(RX was LOW for at least one character
frame time).
3
RO
Receiver Data Framing Error Flag
0 = No Data Framing Error
1 = framing error occurred in data to be read from RX FIFO (The receive character did not have a
valid stop bits).
2
RO
Receiver Data Parity Error Flag
0 = No Data Parity Error
1 = parity error in data to be read from RX FIFO
1
RO
Receiver Overrun Error
0 = No overrun Error
1 = additional data received while the RX FIFO is full. This data should not be transferred into FIFO.
0
RO
Receiver Data Ready Indicator
0 = No data in received in RX FIFO
1 = Data has been received and saved in the RX FIFO
Offset 05H: XON2 character Register (XON2). Accessible when LCR=0xBF and SFR[2]=0. Default=00
Bit
Type
Description
[7:0]
RW
XON2 character
Note: It is reset only when Power-On-Reset.
Offset 06H: Modem Status Register (MSR). Accessible when LCR[7]=0 and MCR[2]=0 and SFR[2]=0. Default=00
Bit
Type
Description
7
RO
CD input status
Normally this bit is the complement of the CD# input.
In the loopback mode this bit is equivalent to MCR[3].
Configuration Registers cont..



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