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PI7C9X760ACLEX bảng dữ liệu(PDF) 29 Page - Diodes Incorporated |
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PI7C9X760ACLEX bảng dữ liệu(HTML) 29 Page - Diodes Incorporated |
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29 / 53 page ![]() 29 www.diodes.com April 2019 Diodes Incorporated PI7C9X760 Document Number DS40305 Rev 6-2 A product Line of Diodes Incorporated PI7C9X760 6 RW Break control bit. 0 = no TX break condition 1 = forces TX to logic 0 to alert a line break condition 5 RW Set forced parity format(if LCR[3]=1) 0 = parity is not forced. 1 = parity bit is forced to high if LCR[4]=0,or low if LCR[4]=1. 4 RW Parity type select. 0 = odd parity is generated(if LCR[3]=1) 1 = even parity is generated(if LCR[3]=1) 3 RW Parity enable when set 2 RW Number of Stop bits 0 = 1 stop bit. 1 = 1.5 stop bits for word length=5, or 2 stop bits for word length=6,7,8 1:0 RW Word length bits: 00 = 5 bits. 01 = 6 bits 10 = 7 bits. 11 = 8 bits Offset 04H: Modem Control Register (MCR). Accessible when LCR[7]=0. Default=00 Bit Type Description 7 RW Clock pre-scaler select. 0 = divide-by-1 clock input 1 = divide-by-4 clock input 6 RW IrDA mode enable when set. 5 RW When set, Xon Any function is enabled and receiving any character will resume transmit operation. The RX character will be loaded into the RX FIFO, unless the RX character is an Xon/Xoff character and receiver software flow control is enabled. 4 RW When set, internal loopback mode is enabled and TX output is looped back to the RX input internally, and MCR[1:0] signals are looped back into MSR[4:5] 3 RW OP2. It is not available as an output pin but can be controlled in Internal Loopback Mode(MCR[4]=1) and is outputed to DCD internally. 2 RW OP1/TCR and TLR enable. In Internal Loopback Mode(MCR[4]=1), it is outputed to RI internally. Otherwise it is used to select between the MSR and TCR registers at offset 0x6 and the SPR and TLR registers at offset 0x7. 1 RW RTS pin control. 0 = force RTS pin High 1 = force RTS pin Low When IN internal loopback mode, it controls MSR[4]. If Auto-RTS is enabled, the RTS pin is controlled by hardware flow control . 0 RW DTR pin control if GPIO5 or GPIO1 is selected as DTR modem pin through IO Control register bit 1 or bit 2: 0 = force DTR pin High 1 = force DTR pin Low When internal loopback mode, it controls MSR[5]. Configuration Registers cont.. Note: MCR[7:5],MCR[3:2] can only be modified if EFR[4]=1. |
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