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PI7C9X760ACLEX bảng dữ liệu(PDF) 27 Page - Diodes Incorporated

tên linh kiện PI7C9X760ACLEX
Giải thích chi tiết về linh kiện  I2C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs
PDF  53 Pages
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nhà sản xuất  DIODES [Diodes Incorporated]
Trang chủ  http://www.diodes.com
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PI7C9X760ACLEX bảng dữ liệu(HTML) 27 Page - Diodes Incorporated

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www.diodes.com
April 2019
Diodes Incorporated
PI7C9X760
Document Number DS40305 Rev 6-2
A product Line of
Diodes Incorporated
PI7C9X760
Offset 01H: Divisor Latch MSB(DLH). Accessible when LCR[7]=1 and LCR!=0xBF. Default=00
Bit
Type
Description
[7:0]
RW
MSB bits of divisor for baud rate generator.
Note: It is reset only when Power-On-Reset.
Offset 02H: Interrupt Identification Register (IIR). Accessible when LCR[7]=0. Default=01
Bit
Type
Description
[7:6]
RO
Mirror the content of FCR[0]
[5:1]
RO
5-bit encoded interrupt.
0
RO
Interrupt status. "1": No interrupt is pending.
"0": An interrupt is pending.
Priority Level
IIR[5]
IIR[4]
IIR[3]
IIR[2]
IIR[1]
IIR[0]
Source of Interrupt
1
0
0
0
1
1
0
Receive Line Status Error
2
0
0
1
1
0
0
Receiver timeout
2
0
0
0
1
0
0
RHR interrupt
3
0
0
0
0
1
0
THR interrupt
4
0
0
0
0
0
0
Modem interrupt
5
1
1
0
0
0
0
Input pin change of state
6
0
1
0
0
0
0
Rx Xoff signal/special character
7
1
0
0
0
0
0
CTS,RTS change from active to inactive
Note: IIR[4] is cleared by Xon detection if the interrupt is caused by Xoff detection, or cleared by a read of the IIR if it is caused by special char detection.
Offset 02H: FIFO Control Register (FCR). Accessible when LCR[7]=0. Default=00
Bit
Type
Description
[7:6]
WO
RX trigger. Sets the trigger level for the RX FIFO
00 = 8 characters
01 = 16 characters
10 = 56 characters
11 = 60 characters
[5:4]
WO
TX trigger. Sets the trigger level for the TX FIFO
00 = 8 spaces
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
3
RO
Reserved
2
WOS
Reset TX FIFO.
0 = No FIFO transmit reset
1 = Clears the contents of Tx FIFO and resets the FIFO level logic.
TSR is not cleared. This bit will return to logic 0 after clearing the FIFO
1
WOS
Reset RX FIFO.
0 = No FIFO receive reset
1 = Clears the contents of Rx FIFO and resets the FIFO level logic.
RSR is not cleared. This bit will return to logic 0 after clearing the FIFO
Configuration Registers cont..



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