L9960 datasheet(43/95 Pages) STMICROELECTRONICS

43 / 95 page

DS11115 Rev 10

43/95

L9960, L9960T

Functional description

The current SR setting is reported by bit "ISR_echo"

Note:

(-) available in the R8 bit position in SPI answer frame 7a.

4.6.3

Voltage slew rate

The voltage slew rate on HS FETs can be set in real time by SPI.

The corresponding read/write bit is "VSR". Only the power transistors not used for

freewheeling are adjustable, the two others are controlled with a preset slew rate.

Note:

(-) available in the R6 bit position in SPI command frame 3.

Voltage Slew rate depends upon the VSR/NOSR bit configuration also on the following

bit/conditions (ILIM_REG, overcurrent or Tj (and TDSR)) as defined in the table below.

The voltage SR setting is reported by bit "VSR_echo".

Note:

(-) available in the R7 bit position in SPI answer frame 7a.

Table 48. ISR_echo

Bit status

Description

Condition

echo ISR SLOW config

echo ISR FAST config

Default value

Table 49. VSR

Bit status

Description

Condition

see table below

default value see table

Reset value

Table 50. Voltage slew rate

Range/ condition

VSR

TDSR

NOSR

Condition

SLOW

Slow dV/dT

FAST (Default at POR)

Fast dV/dT

SR disabled if ILIM_REG = 1

Or NOC = 0

Very fast dv/dt

Slew rate disabled if

tj > OTwam

Very fast dv/dt

Slew rate disabled

Very fast dv/dt

Table 51. VSR_echo

Bit status

Description

Condition

echo VSR SLOW config

echo VSR FAST config

Default value

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