L9960 datasheet(37/95 Pages) STMICROELECTRONICS

37 / 95 page

DS11115 Rev 10

37/95

L9960, L9960T

Functional description

Note:

(-) available in the R9 bit position in SPI answer frame 8a.

The µC should be able to perform a SOPC (Switch-off path check). For that purpose, the

status of each disable line is also provided through SPI status of the followings pins: NDIS,

DIS, VDD5_OV, VDD5_UV.

The status of NDIS and DIS can be monitored by 2 SPI registers:

Note:

(-) available in the R11 bit position in SPI answer frame 8a.

Note:

(-) available in the R10 bit position in SPI answer frame 8a.

4.5.3

Control inputs DIR and PWM

The pins DIR and PWM are internally pulled down. In normal mode, the bridge is controlled

by these two inputs according to the following table:

Note:

A minimum pulse width of 1 µs has to be guaranteed on driving control pins PWM/DIR for

the relative command acknlowdgement by internal logic.

In IN1/IN2 mode, the bridge is controlled by these two inputs according to the table below:

Table 38. NDIS_status

Bit status

Description

Condition

NDIS pin = '0'

NDIS pin = '1'

Table 39. DIS_status

Bit status

Description

Condition

DIS pin = '0'

DIS pin = '1'

Table 40. Normal mode H-bridge input

DIR

PWM

OUT1_HS

OUT1_LS

OUT2_HS

OUT2_LS

Condition

111

Forward

010

Reverse

Freewheeling

Table 41. IN1/IN2 mode H-bridge input

Inputs

Outputs (MOS Driver)

Condition

IN2 (DIR)

IN1 (PWM) OUT1_HS

OUT1_LS

OUT2_HS

OUT2_LS

LS Freewheeling

Forward

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