L9374LF datasheet(34/80 Pages) STMICROELECTRONICS

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Circuit description

L9374LF

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DocID025414 Rev 1

SWT values) the parameters Set-Point 1 (DUTY1 or CUR/DTY1), Set-Point 2 (DUTY2 or

CUR/DTY2) and duration t1 (D_Qx) are programmed (for programming instructions see

section 5.1.5: Duration registers (address 4 and 5)).

Generically, after the SYNC_TRIG the Set-Point 1 is valid for t1 ms. After t1 ms the set-point

controller switches to Set-Point 2 until the next SYNC_TRIG event.

Figure 20. Set-point control example

In this example the RESET_VALUE (and therefore the SPI transfer loop time) is set to 5ms

and the SYNC_VALUE is set to 2.5 ms. This sets the SYNC_TRIG at 2.5 ms after each SPI

transfer. At SYNC_TRIG, the new information received at the previous SPI transfer is

incorporated into the Set-Point Controller.

4.5

Current controller

Two outputs (Q3 & Q4) are equipped with a current controller. The current controller

converts the Set-Point controller output (Current Set Point) into a current level regulated

duty cycle command using a sophisticated algorithm incorporating Load resistance supply

voltage, and recirculation path variances.

The current controller output duty cycle information is calculated using a dedicated load

model in standard Arithmetic Logic Unit (ALU). This model includes the supply voltage, the

recirculation path as well as the load resistance. The load resistance value is programmable

via SPI while the recirculation path and the load supply voltage parameters are measured

by the L9374LF. These measured values are readable via SPI as well.

4.5.1

Load resistance error integration phase

The value of the programmed Load is corrected during the valve actuation. This correction

is called the Error Integration Phase and the resulting value (ISAT_Qx,) is accessible via

SPI (Status registers 8 and 9, Section 5.2.5). ISAT_Qx is an internal value of the current

controller. In an ideal system (without any system tolerances) the first approximation is

determined y the equation:

ISAT RL_real

RL_SPI

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