L9374LF datasheet(25/80 Pages) STMICROELECTRONICS

25 / 80 page

DocID025414 Rev 1

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L9374LF

Circuit description

4.1.4

Address decoder

The address decoder routes incoming data into the appropriate receive buffer and sets up

the appropriate send buffer register to transmit information back to the master (MISO) for

the subsequent SPI communication.

4.1.5

Parity generator

The parity generator completes the output messages with a parity bit. The number of ‘1’s

within an output-transfer has to be odd. Parity is verified prior to the SPICS going high.

4.1.6

Initial MISO information

After initial power on, the first SPI-answer from the L9374LF reflects the Chip-ID

information. Typically, the information will appear as follows:

This information is unique to this device and reflects specific device information relevant

only to ST.

4.1.7

This is a brief reference to the register locations within the L9374LF. Refer to Section 5:

Programmers guide for a more detailed description of each register.

Command buffer (data in)

D10

1010001110000110

Table 28. Command buffer (data_in)

Address(HEX)

Content

Buffer name

Sync-trigger, Reset, and Sync values

SYNC_REG

STW min and max values

STW_V

Configuration register

CONFIG 1

Fast Switch ON gate commands

FSON

Duration Registers doe Q1 /Q2

Duration Q1/Q2

Duration of current 1 Q3 + duration of current 1 Q4

Duration Q3/Q4

Duty cycle 1 Q1

DUTY1_Q1

Duty cycle 2 Q1

DUTY2_Q1

Duty cycle 1 Q2

DUTY1_Q2

Duty cycle 2 Q2

DUTY2_Q2

Current/duty cycle1 Q3

CUR/DTY1_Q3

Current/duty cycle 2 Q3

CUR/DTY2_Q3

Current/duty cycle 1 Q4

CUR/DTY1_Q4

Current/duty cycle 2 Q4

CUR/DTY2_Q4

Current / PWM controller configuration register 2

CONFIG 2

Current / PWM controller configuration register 3

CONFIG 3

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