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L9374LF bảng dữ liệu(PDF) 24 Page - STMicroelectronics

tên linh kiện L9374LF
Giải thích chi tiết về linh kiện  Four channel valve driver
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L9374LF bảng dữ liệu(HTML) 24 Page - STMicroelectronics

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Circuit description
L9374LF
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DocID025414 Rev 1
4.1.2
SPI failure detection
SPI communications sent to the L9374LF that contain errors are ignored. This inaction
includes both the commands given and the data retrieved. That is, commands are ignored
and the initial state of the output is not changed. Also data registers referenced by the
erroneous SPI communication will not be reset.
Figure 12. SPI error handling
Three functions are monitored to discern a correct SPI communication from the master:
1.
Correct number of Clock pulses in SPICLK per transfer.
During each SPICS-low-phase the L9374LF counts the number of positive edges of
SPICLK. If this number is unequal to 16 a SPICLK-error is detected.
2.
Parity check (odd)
The L9374LF detects a parity error if the number of ‘1’s within a transfer is even.
3.
Data-failure monitoring:
This bit is set if the master writes inappropriate data to any of the configuration
registers (2/14/15).
4.1.3
Data transfer
Upon the completion of each 16 bit SPI command (rising edge of SPICS), data is
transferred from the SPI block to the appropriate internal registers. Some internal SPI
registers are reset (such as fault bits) once they are accessed.



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