L9374LF datasheet(59/80 Pages) STMICROELECTRONICS

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L9374LF

Programmers guide

Writing not valid bit combinations generates a SPI-data-failure and causes that specific SPI

command to be ignored and subsequent returning Status Register data to be set to all ‘1’s.

CLKIN input frequency 1MHz / 250kHz (CLKIN_S):

These two bits set the ratio between internal and external clock (SeeChapter 4.2: Clock).

Writing not valid bit combinations generates a SPI-data-failure and causes that specific SPI

command to be ignored and subsequent returning Status Register data to be set to all ‘1’s.

Fast switch off (FSOFF_ALL):

These two bits (D4 & D5) are normally set to ‘01’. With these two bits set to ‘10’ all outputs

are switched off immediately (without regard to the synchronization). When set to active

these bits clear the fast switch on enable (FSON_EN) bit at address 3 and all set points. It is

not possible to activate any output with status FSOFF_ALL = ‘10’ (active). This bit pattern is

also used to initiate the ALU built in self test, or BIST, (for more details on the Built In Self

Test see Chapter 4.8.12: ALU- BIST (Build in self test)).

Writing Not Valid bit combinations generates a SPI-data-failure and causes that specific SPI

command to be ignored and subsequent returning Status Register data to be set to all ‘1’s.

Fast switch on enable (FSON_EN):

This bit (D6) is normally set to ‘0’. Setting this bit (‘1’) enables the SPI ability to drive outputs

directly. With this bit set, writing to address 3 (bits D0 -D3) turns or off outputs Q1 - Q4. All of

the bits in Command Register 3 are reset when FSON_EN is reset (‘0’).

Table 43. Silent valve driver test (SVDT)

Bit 1

Bit 0

Combination

Not valid

Normal condition / no test

Active

Not valid

Table 44. CLKIN_S

Bit 1

Bit 0

Combination

Not valid

250 kHz

1 MHz

Not valid

Table 45. Fast switch off

Bit 1

Bit 0

Combination

Not Valid

Normal condition

Active → all outputs are off

Not Valid

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