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tDr

tSU

tOD

MSB IN

LSB IN

MSB OUT

LSB OUT

SSLn0

input

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

MOSIn

input

MISOn

output

SPI

tDf

tTISS

tTISH

1st frame

2nd frame

DATA

MSB IN

tOD

MSB OUT

tSU

Figure 2.46

SPI timing for TI SSP slave when transmit with no delay between frames

2.3.11

IIC Timing

Table 2.29

IIC timing (1)-1

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_B, SCL1_B, SCL0_C, SDA0_C, SCL0_D, SDA0_D, SCL0_E, SDA0_E, SCL0_F, SDA0_F, SCL1_C, SDA1_C, SCL1_D,

SDA1_D, SCL1_E, SDA1_E.

(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.

(3) Use pins that have a letter appended to their names, for instance _A or _B or _C or _D or _E or _F, to indicate group membership. For

the IIC interface, the AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Min

Max

Unit

Test

conditions

IIC

(Standard mode,

SMBus)

BFCTL.FMPE = 0

SCL input cycle time

tSCL

10 (18) × tIICcyc + 1300

—

Figure 2.47

SCL input high pulse width

tSCLH

5 (9) × tIICcyc

—

SCL input low pulse width

tSCLL

5 (9) × tIICcyc

—

SCL, SDA rise time

tSr

—

1000

SCL, SDA fall time

tSf

—

300

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc ns

SDA input bus free time

tBUF

5 (9) × tIICcyc + 300

—

START condition input hold time

tSTAH

tIICcyc + 300

—

Repeated START condition input

setup time

tSTAS

1000

—

STOP condition input setup time

tSTOS

1000

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

400

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle.

Note:

Values in parentheses apply when INCTL.DNFS[3:0] is set to 0011b while the digital filter is enabled with INCTL.DNFE set to 1.

Note 1. Cb indicates the total capacity of the bus line.

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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