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2.3.7

PDG Timing

Table 2.21

PDG timing

Parameter

Min

Typ

Max

Unit

Test conditions

Operation frequency

—

200

MHz

—

Resolution

—

156

—

GPTCLK = 200 MHz

DNL*1

—

±2.0

—

LSB

—

Note 1. This value normalizes the differences between lines in 1-LSB resolution.

2.3.8

CAC Timing

Table 2.22

CAC timing

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

CAC

CACREF input pulse

width

tPBcyc ≤ tcac*1

tCACREF

4.5 × tcac + 3 × tPBcyc —

—

tPBcyc > tcac*1

5 × tcac + 6.5 × tPBcyc —

—

Note:

tPBcyc: PCLKB cycle.

Note 1. tcac: CAC count clock source cycle.

2.3.9

SCI Timing

Table 2.23

SCI timing (Asynchronous mode)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Note

Input clock cycle

tScyc

—

tTcyc

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

tScyc

—

tTcyc

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

—

Output clock fall time

tSCKf

—

Note:

tTcyc: SCITCLK cycle.

tSCKW

tSCKr

tSCKf

tScyc

SCKn

Note:

n = 0 to 4, 9

Figure 2.32

SCK clock input/output timing

Table 2.24

SCI timing (Simple SPI) (1 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

Min

Max

Unit

Note

SCK clock cycle output

Master

tSPcyc

65536

tTcyc

SCK clock cycle input

Slave

—

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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