R7FA6T2AB3CFM datasheet(46/93 Pages) RENESAS

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Table 2.26

SCI timing (Clock synchronous mode) (2 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

Min

Max

Unit

Note

SCK clock low pulse width

Master

tSPCKWL

0.4

0.6

tSPcyc

Slave

SCK clock rise and fall time

Output

tSPCKr, tSPCKf

—

Input

Data input setup time

Master

High Speed*1

tSU

2.6

—

Default*2

2.8

—

Slave

3.3

—　

Data input hold time

Master

High Speed*1

—

Default*2

—

Slave

—

Data output delay

Master

High Speed*1

tOD

—

Default*2

—

7.3

Slave

High Speed*1

—

Default*2

—

Data output hold time

Master

tOH

—

Slave

—

Data rise and fall time

Output

tDr, tDf

—

Input

—

Note:

tTcyc: SCITCLK cycle.

Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, _C, to indicate group membership. SCI0 is instance

_A, SCI2 and SCI3 are instance _B, SCI1 and SCI9 are instance _C, SCI4 is instance _C and RXD is only PD14.

Note 2. All pins of group membership can be used.

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

SCKn

master select

output

SCKn

slave select input

Note:

n = 0 to 4, 9

Figure 2.33

SCI simple SPI mode clock timing

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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