R7FA6T2AB3CFM datasheet(50/93 Pages) RENESAS

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2.3.10

SPI Timing

Table 2.28

SPI timing (1 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

VCC = 3.0 to 3.6 V, C = 15

VCC = 2.7 to 3.6 V, C = 30

Unit

Note

Min

Max

Min

Max

RSPCK clock cycle

Master

tSPcyc

4096

tTcyc

Slave

—

RSPCK clock high

pulse width

Master

tSPCKWH

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

Slave

0.4

0.6

0.4

0.6

tSPcy

RSPCK clock low

pulse width

Master

tSPCKWL

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

Slave

0.4

0.6

0.4

0.6

tSPcy

RSPCK clock rise

and fall time

Output

tSPCKr,

tSPCKf

—

Input

—

µs

Data input setup

time

Master

High

Speed*1

tSU

—

Default*2　

—

1.3

—

Slave

2.5

—

2.7

—

Data input hold time Master

High

Speed*1

6.2

—

Default*2

—

Slave

2.5

—

2.5

—

SSL setup time

Master

tLEAD

tSPcy

Slave

—

tTcyc

SSL hold time

Master

tLAG

tSPcy

Slave

—

tTcyc

TI SSP SS input

setup time

Slave

tTISS

2.5

—

2.8

—

TI SSP SS input

hold time

Slave

tTISH

2.5

—

2.5

—

TI SSP next-access

time

Slave

tTIND

2 × tTcyc +

SLNDL ×

tTcyc

—

2 × tTcyc +

SLNDL ×

tTcyc

—

TI SSP master SS

output delay

Master

tTISSOD

—

8.9

—

8.9

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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