R7FA6T2AB3CFM datasheet(49/93 Pages) RENESAS

49 / 93 page

Table 2.27

SCI timing (Simple IIC mode)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Note

Simple IIC

(Standard mode)

SCL, SDA input rise time

tSr

—

1000

SCL, SDA input fall time

tSf

—

300

SCL, SDA input spike pulse removal

time

tSP

4 × tTcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

400

Simple IIC (Fast

mode)

SCL, SDA input rise time

tSr

—

300

SCL, SDA input fall time

tSf

—

300

SCL, SDA input spike pulse removal

time

tSP

4 × tTcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

400

Note:

tTcyc: SCITCLK cycle.

Note 1. Cb indicates the total capacity of the bus line.

SDAn

SCLn

VIH

VIL

P*1

S*1

tSf

tSr

tSDAH

tSDAS

tSP

P*1

Test conditions:

VIH = VCC × 0.7, VIL = VCC × 0.3

VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0)

VOL = 0.4 V, IOL = 20 mA (ICFER.FMPE = 1)

Sr*1

Note:

n = 0 to 4, 9

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.38

SCI simple IIC mode timing

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

Page 49 of 93

R7FA6T2AB3CFM bảng dữ liệu(PDF) 49 Page - Renesas Technology Corp

R7FA6T2AB3CFM bảng dữ liệu(HTML) 49 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

bảng dữ liệu tải về

Link URL