VSC8658 datasheet(61/95 Pages) MICROSEMI

61 / 95 page

Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

The following table lists the addresses and register names in the GPIO register page space. These

registers are accessible only when the device register 31 is set to 0x0010.

5.4.1

Reserved GPIO Address Space

The bits in registers 0G to 12G, and 14G of the GPIO register page space are reserved.

5.4.2

SIGDET vs GPIO Control

The SIGDET control register configures GPIO pins 7:0 to be either SIGDET pins for each port or to be

GPIO pins. The following table shows the values that can be written.

Table 52 •

General-Purpose Registers Page Space

0G through 12G

Reserved

13G

SIGDET vs GPIO control

14G

Reserved

15G

GPIO input

16G

GPIO output

17G

GPIO output enable

18G

100BASE-FX control

19G through 30G

Reserved

Table 53 •

SIGDET vs GPIO Control, Address 13G (0x0D)

Bit

Name

Access

Description

Default

15:14

SIGDET7 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

13:12

SIGDET6 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

11:10

SIGDET5 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

9:8

SIGDET4 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

7:6

SIGDET3 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

5:4

SIGDET2 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

3:2

SIGDET1 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

1:0

SIGDET0 control

R/W

00 = Normal SIGDET operation

01, 10 = Reserved

11 = Controlled by MII registers 15G to 17G

0x00

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