VSC8658 datasheet(48/95 Pages) MICROSEMI

48 / 95 page

Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

Note When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the

state of bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted.

5.2.21

Interrupt Status

The status of interrupts already written to the device are available for reading from register 26 in the main

registers space. The following table shows the readouts you can expect.

Inline powered device (PoE) detect mask

R/W

This is a sticky bit.

1 = Enabled.

8:5

Reserved

AMS media changed mask

R/W

This is a sticky bit.

1 = Enabled.

Reserved

Link speed downshift detect mask

R/W

This is a sticky bit.

1 = Enabled.

Master/Slave resolution error mask

R/W

This is a sticky bit.

1 = Enabled.

Reserved

Table 30 •

Interrupt Status, Address 26 (0x1A)

Bit

Name

Access

Description

Default

Interrupt status

This is a self-clearing bit.

1 = Interrupt pending.

Speed state change status

This is a self-clearing bit.

1 = Interrupt pending.

Link state change status

This is a self-clearing bit.

1 = Interrupt pending.

FDX state change status

This is a self-clearing bit.

1 = Interrupt pending.

Auto-negotiation error status

This is a self-clearing bit.

1 = Interrupt pending.

Auto-negotiation complete status

This is a self-clearing bit.

1 = Interrupt pending.

Inline powered device detect status

This is a self-clearing bit.

1 = Interrupt pending.

8:5

Reserved

AMS media changed status

This is a self-clearing bit.

1 = Interrupt pending.

3Reserved

Link speed downshift detect status

This is a self-clearing bit.

1 = Interrupt pending.

Master/Slave resolution error status

This is a self-clearing bit.

1 = Interrupt pending.

0Reserved

Table 29 •

Interrupt Mask, Address 25 (0x19) (continued)

Bit

Name

Access

Description

Default

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