VSC8658 datasheet(43/95 Pages) MICROSEMI

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Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

5.2.14

1000BASE-T Status Extension 2

The second status extension register is at address 17 in the device main registers space. It provides

information about another set of parameters associated with 1000BASE-T communications. For

information about the first status extension register, see Table 23, page 34.

5.2.15

Bypass Control

The bits in the Bypass Control register in the VSC8658 device control aspects of functionality in effect

when the device is disabled so that traffic can bypass it in your design. The following table shows the

settings available.

Table 24 •

1000BASE-T Status Extension 2, Address 17 (0x11)

Bit

Name

Access

Description

Default

1000BASE-T

descrambler

1 = Descrambler locked.

1000BASE-T lock

error

This is a self-clearing bit.

1 = Lock error detected.

1000BASE-T

disconnect state

This is a self-clearing bit.

1 = PHY 1000BASE-T link disconnect

detected.

1000BASE-T current

link status

1 = PHY 1000BASE-T link active.

1000BASE-T receive

error

This is a self-clearing bit.

1 = Receive error detected.

1000BASE-T transmit

error

This is a self-clearing bit.

1 = Transmit error detected.

1000BASE-T SSD

error

This is a self-clearing bit.

1 = Start-of-stream delimiter error detected.

1000BASE-T ESD

error

This is a self-clearing bit.

1 = End-of-stream delimiter error detected.

1000BASE-T carrier

extension error

This is a self-clearing bit.

1 = Carrier extension error detected.

6:0

Reserved

Table 25 •

Bypass Control, Address 18 (0x12)

Bit

Name

Access

Description

Default

Transmit disable

R/W

1 = PHY transmitter disabled.

14:9

Reserved

1000BASE-T

transmitter test clock

R/W

1 = Enabled.

Auto MDI-X at forced

10/100

R/W

This is a sticky bit.

1 = Disable Auto MDI-X at forced 10/100

speeds.

6Reserved

Disable pair swap

correction

R/W

This is a sticky bit.

1 = Disable the automatic pair swap correction.

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