VSC8658 datasheet(47/95 Pages) MICROSEMI

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Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

Note When bits 5:4 are set to Jumbo Packet mode, the default maximum packet values are based on

100 ppm driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY

as specified in the bit description results in a higher Jumbo packet length.

5.2.20

Interrupt Mask

The bits in register 25 control the device interrupt mask. The following table shows the settings available.

11:9

Reserved

8:7

SGMII input preamble R/W

This is a sticky bit.

00 = No SGMII preamble required.

01 = One-byte SGMII preamble required.

10 = Two-byte SGMII preamble required.

11 = Reserved.

SGMII output

preamble

R/W

This is a sticky bit.

0 = No SGMII preamble.

1 = Two-byte SGMII preamble.

5:4

Jumbo packet mode

R/W

This is a sticky bit.

00 = Normal IEEE 1.5 kB packet length.

01 = 9 kB jumbo packet length (12 kB with

60 ppm or better reference clock).

10 = 12 kB jumbo packet length (16 kB with

70 ppm or better reference clock).

11 = Reserved.

3:1

100BASE-TX

transmitter amplitude

control

R/W

011 = +3 Amplitude setting (largest).

010 = +2 Amplitude setting.

001 = +1 Amplitude setting.

000 = Default amplitude.

111 = –1 Amplitude setting.

110 = –2 Amplitude setting.

101 = –3 Amplitude setting.

100 = –4 Amplitude setting (smallest).

000

1000BASE-T

connector loopback

R/W

1 = Enabled.

Table 29 •

Interrupt Mask, Address 25 (0x19)

Bit

Name

Access

Description

Default

MDINT interrupt status enable

R/W

This is a sticky bit.

1 = Enabled.

Speed state change mask

R/W

This is a sticky bit.

1 = Enabled.

Link state change mask

R/W

This is a sticky bit.

1 = Enabled.

FDX state change mask

R/W

This is a sticky bit.

1 = Enabled.

Auto-negotiation error mask

R/W

1 = Enabled.

Auto-negotiation complete mask

R/W

This is a sticky bit.

1 = Enabled.

Table 28 •

Extended PHY Control 2, Address 24 (0x18) (continued)

Bit

Name

Access

Description

Default

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