IMX7ULPIECB2 datasheet(8/112 Pages) NXP

8 / 112 page

Table 1. i.MX 7ULP modules list (continued)

Block Name

Block Mnemonic

Subsystem

Power

Domain

Brief description

format. The ADC can achieve 1

microsecond conversion rate.

Asynchronous

Wakeup Interrupt

Controller

AWIC

System Control

The Asynchronous Wakeup Interrupt

Controller (AWIC) module is capable of

interrupt detection and wake-up of a

processor when it is in low power mode.

Bit Manipulation

Engine

BME

Multicore peripherals

and resource domain

control submodules

The Bit Manipulation Engine (BME)

provides hardware support for atomic

read-modify-write memory operations to

the peripheral address space. This

architectural capability is also known as

"decorated storage" as it defines a

mechanism for providing additional

semantics for load and store operations

to memory-mapped peripherals beyond

just the reading and writing of data

values to the addressed memory

locations.

Comparator

CMP0-1

Analog

DGO

The (CMP) module provides a circuit for

comparing two analog input voltages.

The comparator circuit is designed to

operate across the full range of the

supply voltage (rail to rail operation).

Cross Trigger Matrix CTM

Debug

Cross Trigger Matrix (CTM) is a

component of the Embedded Cross

Trigger (ECT), which is key in the

multicore debug strategy. The CTM

receives signals from various sources

(i.e. cores and peripherals) and

propagates or routes them to the

different debug resources of the SoC.

Those debug resources can include

time stamping capability, real-time

trace, triggers and debug interrupts.

Cryptographic

Acceleration and

Assurance

CAAM

Security

Cryptographic Acceleration and

Assurance Module (CAAM) is a

multifunction accelerator that supports

the cryptographic functions common in

many security protocols. This includes

AES128, AES256, DES, 3DES, SHA1,

SHA224, SHA256, and a random

number generator with a true entropic

seed. CAAM includes a DMA engine

that is descriptor based to reduce

processor-accelerator interaction.

Security feature clear keys and

memories when on-chip security

monitor detects tampering. The Secure

RAM is implemented and provides

secure storage of sensitive information

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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