IMX7ULPIECB2 datasheet(6/112 Pages) NXP

6 / 112 page

Table of Contents

1 i.MX 7ULP modules list......................................................... 7

2 Clocking................................................................................ 21

2.1

Introduction..................................................................21

2.2

Clock distribution......................................................... 22

2.3

External clock sources.................................................23

2.4

Oscillators....................................................................23

2.5

Internal clock sources..................................................23

3 Application domain (implementing ARM Cortex-A7).............24

3.1

Memory system—application domain..........................24

3.1.1

Internal memory (application domain)...........24

3.1.2

Multi Mode DDR Controller (MMDC).............24

3.1.3

eMMC............................................................25

3.2

Peripherals—application domain.................................25

3.2.1

Graphics processor human machine

interfaces.......................................................25

3.2.2

Security—application domain........................26

3.2.3

Timers—application domain..........................27

3.2.4

Connectivity and communications—

applications domain...................................... 27

4 Real-time domain (implementing ARM Cortex-M4).............. 28

4.1

Memory system—real-time domain.............................28

4.1.1

Internal memory—real-time domain..............28

4.1.2

QuadSPI flash............................................... 28

4.2

Peripherals—real-time domain.................................... 28

4.2.1

Analog—real-time domain.............................28

4.2.2

Connectivity and communications—real-

time domain...................................................29

5 System control modules........................................................29

5.1

JTAG—system control.................................................29

5.2

JTAG device identification register.............................. 29

5.3

Oscillators and PLLs....................................................30

5.3.1

System oscillator (SYS OSC)........................30

5.3.2

Real-Time Clock Oscillator (RTC OSC)........ 30

5.3.3

USB PLL....................................................... 30

5.3.4

Fixed Frequency PLL (Fixed-freq PLL)......... 30

5.3.5

Fractional-N PLL (FracN PLL).......................31

5.4

Power Management.................................................... 31

5.4.1

Digital PMC................................................... 31

5.4.2

Analog power management controller

(Analog PMC)................................................31

6 i.MX 7ULP LDO Bypass versus LDO-enabled modes.......... 32

6.1

Real-time domain LDO Enabled mode........................32

6.2

Application domain LDO Enabled mode......................32

6.3

Application domain LDO BYPASS mode.................... 32

7 System specifications............................................................33

7.1

Ratings........................................................................ 33

7.1.1

Thermal handling ratings...............................33

7.1.2

Moisture handling ratings.............................. 33

7.1.3

ESD handling ratings.................................... 33

7.1.4

Absolute maximum ratings............................34

7.1.5

Recommended operating conditions—

system...........................................................35

7.1.6

Estimated maximum supply currents............ 39

7.2

System clocks..............................................................40

7.2.1

Clock modules...............................................40

7.2.2

Core, platform, and system bus clock

frequency limitations..................................... 43

7.2.3

Peripheral clock frequencies......................... 44

7.2.4

PLL PFD output.............................................47

7.2.5

Audio tunable clock....................................... 48

7.3

Power sequencing—system........................................ 49

7.3.1

Power-on sequencing................................... 49

7.3.2

Power-off sequencing................................... 50

7.4

Requirements for unused interfaces............................50

7.5

Electrical Characteristics and Thermal Specifications.51

7.5.1

AC electrical characteristics.......................... 51

7.5.2

Nonswitching electrical characteristics..........52

7.5.3

Switching electrical characteristics................53

7.5.4

Debug and trace modules............................. 55

7.5.5

Thermal specifications.................................. 59

8 Specifications—application domain...................................... 60

8.1

Peripheral operating requirements and behaviors.......60

8.1.1

DDR timing—application domain.................. 60

8.1.2

Ultra-high-speed SD/SDIO/MMC host

interface (uSDHC) AC timing—application

domain.......................................................... 60

8.1.3

Flexbus switching specifications................... 66

8.1.4

Display, Video, and Audio Interfaces............ 69

8.1.5

Timer specifications—application domain.....70

8.1.6

Connectivity and communications

specifications—application domain............... 70

9 Specifications—real-time domain..........................................79

9.1

Power sequencing—real-time domain.........................79

9.2

Peripheral operating requirements and behaviors—

real-time domain..........................................................80

9.2.1

QuadSPI AC specifications........................... 80

9.2.2

Analog modules............................................ 84

9.2.3

Timer specifications—real-time domain........ 92

9.2.4

Connectivity and communications

specifications—real-time domain.................. 92

10 Package information and contact assignments.....................96

10.1 BGA, 14 x 14 mm, 0.5 mm pitch (VP suffix)................ 96

10.1.1

14 x 14 mm package case outline.................96

10.1.2

14 x 14 mm, 0.5 mm pitch, ball map............. 98

10.1.3

14 x 14 mm power supply and functional

contact assignments..................................... 100

11 Revision History.................................................................... 108

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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