IMX7ULPIECB2 datasheet(44/112 Pages) NXP

44 / 112 page

Table 14. Maximum A7 system clock frequencies1 (continued)

Configuration

A7 Core

(MHz)

NIC0 (MHz)2

GPU-3D/

GPU-2D (MHz)

DDR (MHz)2 NIC1 (MHz) A7 System IP

Bus (MHz)

eMMC

HSRUN

650

400

400 (GPU-2D)/

650 (GPU-3D)

271.5

200

100

HS400

mode

VLPR

Not operational Not

operational

(DDR in self-

refresh

mode)

Only 24

MHz

compliant

cards

1. The maximum operating frequency of a given clock must also observe the clock ratio restrictions described in this

section

2. NIC0 and DDR are derived from the same clock.

NOTE

DGO peripherals on the M4 core use the cm4.divslow_clk,

configured by SCG_xCCR[DIVSLOW] in all the modes, with

the maximum frequency of 25 MHz.

Table 15. Maximum M4 system clock frequencies1

Configuration

M4 Core/ Platform

(MHz)

Platform (MHz)

M4 System IP Bus

(MHz)

Slow clock (MHz)

RUN

120

HSRUN

200

100

VLPR

1. The maximum operating frequency of a given clock must also observe the clock ratio restrictions described in this

section

7.2.3 Peripheral clock frequencies

The following table lists peripheral clock frequencies and the indication of platform and

IP bus clocks. Some peripherals have a local clock generator that can further divide the

clock, as required, for the desired serial rate.

Table 16. Peripheral clock frequencies

Module

A7 Fast

Platform

Clk

A7 Slow

Platform

Clk

A7 System

IP Bus Clk

M4 Platform

Clk

M4 System

IP Bus Clk

Peripheral

Clock (MHz)

Notes

AIPS-Lite

Yes

Table continues on the next page...

System specifications

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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