IMX7ULPIECB2 datasheet(71/112 Pages) NXP

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8.1.6.1 LPUART

See General switching timing specifications.

8.1.6.2 Inter-Integrated Circuit Interface (I2C) timing

Table 37. I 2C timing (Standard, Fast, and Fast Plus modes)

Parameter

Symbol

Standard Mode

Fast Mode

Fast-mode Plus

Unit

Min

Max

Min

Max

Min

Max

SCL Clock Frequency

fSCL

100

400

1000

kHz

Hold time (repeated) START

condition. After this period, the

first clock pulse is generated.

tHD; STA

—

0.6

—

0.26

—

µs

LOW period of the SCL clock

tLOW

4.7

—

1.3

—

0.5

—

µs

HIGH period of the SCL clock

tHIGH

—

0.6

—

0.26

—

µs

Set-up time for a repeated

START condition

tSU; STA

4.7

—

0.6

—

0.26

—

µs

Data hold time for I2C bus

devices

tHD; DAT

3.452

0.91

—

µs

Data set-up time

tSU; DAT

2504

—

1002, 5

—

Rise time of SDA and SCL

signals

—

1000

+0.1Cb6

300

+0.1Cb7

120

Fall time of SDA and SCL

signals

—

300

+0.1Cb5

300

+0.1Cb5

120

Set-up time for STOP condition tSU; STO

—

0.6

—

0.26

—

µs

Bus free time between STOP

and START condition

tBUF

4.7

—

1.3

—

0.5

—

µs

Pulse width of spikes that must

be suppressed by the input filter

tSP

N/A

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and

SCL lines.

2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

3. Input signal Slew = 10 ns and Output Load = 50 pF

4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax

+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is

released.

6. Cb = total capacitance of the one bus line in pF.

7. Cb = total capacitance of the one bus line in pF.

Specifications—application domain

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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