IMX7ULPIECB2 datasheet(63/112 Pages) NXP

tên linh kiện	IMX7ULPIECB2

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4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

8.1.2.2 eMMC4.4/4.41 (dual data rate) AC timing

The following figure shows the timing of eMMC4.4/4.41, and the table lists the

eMMC4.4/4.41 timing characteristics. Note that only DATA is sampled on both edges

of the clock (not applicable to CMD).

Figure 12. eMMC4.4/4.41 timing

Table 31. eMMC4.4/4.41 interface timing specifications

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (eMMC4.4/4.41

DDR)

fPP

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

-3.3

3.6

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD3

uSDHC Input Setup Time

tISU

7.3

—

SD4

uSDHC Input Hold Time

tIH

1.0

—

8.1.2.3 HS200 mode timing

The following figure depicts the timing of HS200 mode, and the subsequent table lists

the HS200 timing characteristics.

Specifications—application domain

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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