TMS320F28375DPZP datasheet(192/226 Pages) TI

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9.7 Control Law Accelerator

The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch mechanism,

and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or a peripheral such

as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a

task completes, the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next

highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP,

Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between

the main CPU and the CLA.

Figure 9-2 shows the CLA block diagram.

CPU Read Data Bus

MR0(32)

MVECT1(16)

MIFR(16)

MPC(16)

MIER(16)

MIFRC(16)

MIRUN(16)

MR1(32)

MR3(32)

MAR0(16)

CPU Read/Write Data Bus

CLA Execution

CLA Control

MSTF(32)

PIE

CLA Program

Memory (LSx)

CLA Data

Memory (LSx)

SYSCLK

CLA Clock Enable

SYSRSn

MR2(32)

MAR1(16)

MIOVF(16)

MICLR(16)

MCTL(16)

MICLROVF(16)

LUF

CLA Message

RAMs

Shared

Peripherals

MEALLOW

C28x

CPU

INT11

INT12

MVECT2(16)

MVECT3(16)

MVECT4(16)

MVECT5(16)

MVECT6(16)

MVECT7(16)

MVECT8(16)

LSxMSEL[MSEL_LSx]

LSxCLAPGM[CLAPGM_LSx]

CLA Program Bus

MPERINT1

MPERINT8

CLA_INT1

CLA_INT8

LVF

From

Shared

Peripherals

Figure 9-2. CLA Block Diagram

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

www.ti.com

192

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