TMS320F28375DPZP datasheet(132/226 Pages) TI

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8.11.2.2 ePWM Electrical Data and Timing

Section 8.11.2.2.1 shows the PWM timing requirements and Section 8.11.2.2.2 shows the PWM switching

characteristics.

8.11.2.2.1 ePWM Timing Requirements

MIN(1)

MAX

UNIT

f(EPWM)

Frequency, EPWMCLK(2)

100

MHz

tw(SYNCIN)

Sync input pulse width

Asynchronous

2tc(EPWMCLK)

cycles

Synchronous

2tc(EPWMCLK)

cycles

With input qualifier

1tc(EPWMCLK) + tw(IQSW)

cycles

(1)

For an explanation of the input qualifier parameters, see Section 8.9.6.2.1.

(2)

For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

8.11.2.2.2 ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

tw(PWM)

Pulse duration, PWMx output high/low

tw(SYNCOUT)

Sync output pulse width

8tc(SYSCLK)

cycles

td(TZ-PWM)

Delay time, trip input active to PWM forced high

Delay time, trip input active to PWM forced low

Delay time, trip input active to PWM Hi-Z

8.11.2.2.3 Trip-Zone Input Timing

Section 8.11.2.2.3.1 shows the trip-zone input timing requirements. Figure 8-52 shows the PWM Hi-Z

characteristics.

8.11.2.2.3.1 Trip-Zone Input Timing Requirements

MIN(1)

MAX

UNIT

tw(TZ)

Pulse duration, TZx input low

Asynchronous

1tc(EPWMCLK)

cycles

Synchronous

2tc(EPWMCLK)

cycles

With input qualifier

1tc(EPWMCLK) + tw(IQSW)

cycles

(1)

For an explanation of the input qualifier parameters, see Section 8.9.6.2.1.

PWM

(B)

(A)

EPWMCLK

w(TZ)

d(TZ-PWM)

A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.

Figure 8-52. PWM Hi-Z Characteristics

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D

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