PRT2011CVL5A datasheet(76/112 Pages) NXP

76 / 112 page

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Electrical Characteristics

Figure 48 shows MII transmit signal timings. Table 65 describes the timing parameters (M5–M8) shown

in the figure.

Figure 48. MII transmit signal timing diagram

1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.9.4.1.3

MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)

Figure 49 shows MII asynchronous input timings. Table 66 describes the timing parameter (M9) shown in

the figure.

Figure 49. MII asynchronous inputs timing diagram

1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

Table 65. MII transmit signal timing

Characteristic1

Min.

Max.

Unit

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

5—

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—20

ENET_TX_CLK pulse width high

35%

65%

ENET_TX_CLK period

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

Table 66. MII asynchronous inputs signal timing

Characteristic

Min.

Max.

Unit

M91

ENET_CRS to ENET_COL minimum pulse width

1.5

—

ENET_TX_CLK period

ENET_TX_CLK (input)

ENET_TX_DATA3,2,1,0

ENET_TX_ER

ENET_TX_EN

(outputs)

ENET_CRS, ENET_COL

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